1. Field of the Invention
The present invention relates to a ferroelectric memory, and more specifically to a sample matrix-type ferroelectric memory that uses only a ferroelectric capacitor and does not have a cell transistor. The present invention further relates to an electronic apparatus provided with this ferroelectric memory.
2. Description of Related Art
Ferroelectric memory has undergone rapid development in recent years as a form of nonvolatile memory employing a ferroelectric substance. Typically, a ferroelectric capacitor is formed by employing an oxidized ferroelectric material as the capacitor insulating film, and is used as a non-volatile memory by storing data according to the polarization direction of the ferroelectric capacitor.
In the usual ferroelectric memory, the peripheral circuit for selectively carrying out the writing and reading out of data to and from a memory cell and the memory cell are formed in close proximity to one another. As single cell therefore has a large area, it was difficult to improve the degree of integration in the memory cell and increase the memory capacity.
In order to achieve greater integration and higher capacity, a ferroelectric memory was therefore proposed in which a memory cell array is formed that is composed of first signal electrodes having of stripe-type electrodes which wiring is parallel, second signal electrodes which wiring is in parallel and in a direction which is perpendicular to the direction of the rows of first signal electrodes, and a ferroelectric layer disposed in between the aforementioned first and second signal electrodes at the areas of intersection therebetween, wherein the memory cells in this memory cell array are arranged in the form of a matrix (see Japanese Patent Application, First Publication No. Hei 9-128960).
When a voltage is impressed on a given selected cell in a ferroelectric memory composed of this type of memory cell array, however, a voltage is also impressed on non-selected cells. In order to minimize this effect, a method has been proposed in which a voltage Va is impressed on the selected cell and a voltage Va/3 or −Va/3 is impressed on non-selected cells, this method being accomplished by impressing, for example, a voltage Va on the selected first signal electrode, a voltage Va/3 on the non-selected first signal electrodes, a voltage 0 on the selected second signal electrode, and a voltage 2Va/3 on the non-selected second signal electrodes (see Japanese Patent Application, First Publication No. Hei 9-128960). Accordingly, a domain inversion must occur at Va but must not occur at Va/3 in the ferroelectric layer. In other words, the polarization-electric field (P-E) hysteresis curve must have angularity.
In the usual structure of ferroelectric memory, the memory cell portion is formed on top of a SiO2 protecting layer that is formed on the peripheral circuit that contains the MOS transistor. It is therefore not possible to control the orientation of the ferroelectric layer, and so, the angles that are formed by the impressed electric fields and the polarization axes of each crystal grain vary from one another. As a result, variation also arises in the voltage impressed when each crystal grain undergoes domain inversion, which leads to problematic deterioration in the angularity of the hysteresis curve.